MOSFETs (metal oxide semiconductor FETs) and MISFETs (metal-insulator semiconductor FETs) are devices essential to fabrication of semiconductor integrated circuits (ICs), large scale integrated circuits (LSIs), and very-large-scale integrated circuits (VLSIs). These MOSFETs and MISFETs are collectively referred to as MISFETs herein. Devices having increasingly smaller dimensions and devices having increasingly higher speeds of operation have been manufactured. With these trends, MISFETs have been improved and varied.
The MISFET which is considered to be in the most advanced stage is a lightly doped drain (LDD) MISFET. The structure of this device is schematically shown in FIG. 1. The feature of the MISFET of this structure is that the concentrations of the doped regions formed on the substrate such as source and drain vary relatively continuously and, therefore, a large electric field is not produced at the boundary between each doped region and the neighboring channel region. For example, in the structure shown in FIG. 1, the conductivity type changes frequently in going from a source electrode 7 to a drain electrode 6 through a first source 2 of n.sup.+ -type, a second source region 3 of n.sup.- -type, a channel region 8 of p.sup.- -type, a second drain region 4 of n.sub.- -type, and a first drain region 5 of n.sup.+ -type. For this reason, the electric field set up at the boundary between the channel region and each doped region has a mild gradient. Hence, the carriers are less likely to be accelerated excessively in this region. Consequently, less defects are produced in the semiconductors and in the gate-insulating film. This permits the LDD MISFET to be used for a longer time than is the conventional MISFET.
In the typical LDD MISFET shown in FIG. 1, some problems take place if the device is fabricated in small size. One typical problem is that the doped regions and the gate electrode are overlapped. Another typical problem is the concentration of the electric field between the successive doped regions immediately under the gate-insulating film. The former problem is associated with the process. Usually, each doped region is formed by ion implantation. In particular, dopant ions are implanted into the substrate by a self-aligning process, using the gate electrode as a mask. Ideally, therefore, it is impossible that the gate electrode and the doped regions are overlapped. In practice, however, dopant ions go round and arrive under the gate electrode. It is considered that the main cause for this is that implanted dopant ions are scattered secondarily by the lattices. This effect becomes larger as the energy of the incident ions increases. Also, the effect becomes more conspicuous as the width of the gates decreases, i.e., as the channel length decreases. Owing to the overlap, the parasitic capacitance between the gate electrode and the neighboring doped region increases, and the speed of operation of the MISFET drops.
The typical LDD MISFET shown in FIG. 1 also suffers from the latter problem. Specifically, with the shape of doped region as shown in FIG. 1, if a voltage is applied between the source and drain, the electric field is concentrated at points A and B. The point A is the front end of the second source region. The point B is the front end of the second drain region. Carriers most accelerated run between these two points. Since the points A and B are located immediately under the gate-insulating film, this film is often damaged. Because the gate-insulating film is damaged by the accelerated carriers, the film forms a charge-capturing center. Where the film is damaged severely, it is impossible to control the carries passing through the channel region by the gate electrode. Especially, it is necessary that the gate insulating film be made thinner roughly in proportion to the channel length. A microelectronic MISFET having a channel length less than 0.5 .mu.m has an extremely thin gate insulating film having a thickness as small as tens of nanometers. Consequently, even if defects having dimensions on an atomic scale exist, the characteristics of the MISFET are affected.
An LDD MISFET which has been devised to solve the foregoing problems is shown in FIG. 2(a). This device differs from the device shown in FIG. 1 in that the point A at the front end of the second source region and the point B at the front end of the second drain region are remote from the gate insulating film. Therefore, damage to the gate-insulating film which would otherwise be caused by concentration of the electric field at these two points can be prevented. As can be seen from FIG. 2(a), a considerable distance exists between the electrode and the doped region, although they are overlapped. Hence, the parasitic capacitance is reduced.
The LDD MISFET of this construction is fabricated by implanting dopant ions obliquely. However, where the channel length is less than 0.5 .mu.m, high production yield cannot be maintained because of difficulties with the production. In particular, in order to manufacture MISFETs of this structure with high reproducibility, the energy to which implanted dopant ions are accelerated must be controlled accurately. Also, it is necessary to prepare an ion source emitting ions having homogeneous energy; otherwise, ions implanted obliquely would enter deeper than expected. As a result, neighboring doped regions would be connected to each other, as shown in FIG. 2(b). This tendency becomes more conspicuous as the channel length decreases.
In conclusion, it is industrially difficult to make the channel lengths of the conventional LDD MISFETs including the improved type shown in FIG. 2 less than 0.5 .mu.m, especially less than 0.3 .mu.m. MISFETs having channel lengths less than 0.3 .mu.m are known as quarter micron MISFETs.